Workshop 14: Parallel Computer Architecture
Programme Committee:
General Chair. Mateo Valero
(UPC Barcelona, Spain),
mateo@ac.upc.es
Local Chair. David Snelling
(FECIT, UK),
snelling@fecit.co.uk
Vice Chair. Olivier Temam
(University of Versaille, France),
Olivier.Temam@prism.uvsq.fr
Vice Chair. Nigel Topham
(University of Edinburgh, UK),
npt@dcs.ed.ac.uk
Vice Chair. Rupert Ford
(University of Manchester, UK),
rupert@cs.man.ac.uk
Description:
Parallel computer architecture is concerned with how future computer
systems should be designed to meet the performance demands of emerging
applications through parallelism. While microprocessors today exploit
instruction-level parallelism, parallel computer architecture is mainly
concerned with how we use microprocessors as building blocks to exploit
coarser grain parallelism at the thread level. Important architectural
issues are how to design parallel computer systems that allow for efficient
coordination and communication inside the system.
The scope of this workshop will include (but is not limited to) parallel
computer architectures (general-purpose as well as special-purpose), the
impact of emerging microprocessor architectures on parallel computer
architectures, innovative memory designs to hide and reduce the access
latency, and multi-threading. Papers will be expected to cover
architectural ideas, analysis and modelling, or practical implementations
and their relation to the demands by current and emerging application
domains.
This workshop also emphasizes design automation of electronic systems.
Design automation currently supports the design of complex domain- or
application-specific systems, such as wireless communication, multimedia
processing, computer networking, telecommunication, and automotive
electronics systems. Due to the high demands on the processing power in
these embedded application areas, parallelism must be exploited to meet
real-time requirements. Design automation has to provide techniques for
mapping specifications onto systems which, in general, will be comprised of
a number of processors and special hardware components working in parallel.
Papers are invited that cover techniques for supporting concurrency,
scheduling, mapping a single application onto multi-processor
architectures, and hardware/software interface synthesis.
Topics of interest include:
- parallel architectures
- caches
- multi-threading
- innovative memories
- latency tolerance
- application-specific parallel architectures:
- design automation for parallel custom computing on FPGAs, systolic arrays,
- aspects of parallelism in retargetable code generation, application-specific
instruction sets,
- mapping algorithms onto parallel VLSI architectures
- design automation for parallel heterogeneous VLSI systems:
- specification and models of computation, scheduling and communication synthesis,
- exploitation of concurrency in hardware-software co-design, storage
and power optimization